The present invention relates to a latch circuit which is so arranged as to hold a logic signal in response to a control pulse.
A shift-register may consist of a plurality of D-type flip-flops. FIG. 1 shows a known D-type flip-flop, which is comprised of a master latch circuit 10 for holding an input signal from a terminal IN, and a slave latch circuit 12 for holding an output signal from the latch circuit 10. The latch circuit 10 has a transfer gate 14 to which a logic signal to be held with a prescribed timing is supplied, another transfer gate 16 connected in series to this transfer gate 14, and a serial circuit of inverters 18, 20 which is connected in parallel to the other transfer gate 16. The slave latch circuit 12 has transfer gates 22, 24 and inverters 26, 28 which are assembled in the same manner as in the latch circuit 10. The transfer gates 14, 16, 22, 24 control the passing of respective input signals in accordance with clock pulses .phi., .phi. which are opposite to each other in phase. Each of the transfer gates 14, 24 is a parallel circuit comprised of an n-channel MOS transistor supplied with clock pulse .phi. at its gate, and a p-channel MOS transistor connected in parallel thereto and supplied with clock pulse .phi. at its gate. Each of the transfer gates 16, 22 is similarly constituted by a parallel circuit comprised of an n-channel MOS transistor supplied with clock pulse .phi. at its gate, and a p-channel MOS transistor supplied with clock pulse .phi. at its gate. The transfer gates 14, 16 are in such a relationship that, when one of them is kept conductive, the other is kept nonconductive. Transfer gate 22 is rendered conductive when transfer gate 16 is kept conductive. On the other hand, transfer gate 24 is rendered conductive when transfer gate 22 is kept nonconductive. Each of the inverters 18, 20, 26 and 28 has a p-channel MOS transistor and an n-channel MOS transistor, both of which operate in a complementary fashion.
However, the above-mentioned flip-flop has the following drawbacks. First of all, said flip-flop is composed of a relatively large number of transistors. For this reason, when the shift-register is formed on a semiconductor chip, for example, a large part of the chip area is occupied by the shift-register, disadvantageously. Further, the noise margin and the power source voltage margin of each latch circuit 10 or 12 are determined by the threshold voltages of the transistors involved. For this reason, when one of these two margins is set large, the other margin becomes small. Further, with the above-mentioned flip-flop all of the transistors 14, 16, 22 and 24 may be instantaneously rendered conductive, due to a slight displacement between a rising of clock pulse .phi. and a falling of clock pulse .phi.. At this time, the flip-flop falls into a state of racing, wherein an unstable logic signal is output.